Figure 6.
The diagram illustrates a D D P Transformer architecture composed of sequential blocks. An input x sub 0 passes through block 1 to x sub i minus 1, then enters block sub i. Inside block sub i, two branches with shift equals 0, and shift equals p underscore size over 2 perform Patches extraction, Image 2 Tokens, Position Embedding, and Transformer operations, followed by concatenation C and Point Wise Convolution, G e L U, and Tokens 2 Image to produce x sub i. Outputs pass through subsequent blocks to block sub-n with skip connections shown by plus symbols. A lower pathway shows F B P linking projection and image domains with additional blocks and skip connections. A legend defines block sub i as the i-th D D P Transformer Block, Input Projection, Output Projection, F B P, Skip Connection, and Concatenate.DDPTransformer (Li et al., 2022)