Figure 4
The schematic presents an L S T M memory cell enclosed by a dashed boundary. The previous cell state, C subscript t minus 1, enters from the left along the upper horizontal path. At the forget gate, a sigma function receives the previous hidden state, h subscript t minus 1, and the current input, X subscript t. Its output passes to a multiplication node on the cell state path. The input gate contains a sigma function and a hyperbolic tangent function supplied by h subscript t minus 1 and X subscript t. Their outputs meet at a multiplication node, then pass upward to an addition node, where they combine with the retained previous cell state. The updated cell state continues right as C subscript t. At the output gate, the updated cell state passes through a hyperbolic tangent function. A sigma function receives h subscript t minus 1 and X subscript t, and its output multiplies the transformed cell state. The result exits to the right as h subscript t and also upwards as h subscript t. Arrows indicate the direction of information flow through all gates and operations.Architecture of a LSTM