MODELING OF VLSI INTERCONNECT

Digital systems utilize frequencies into the GHz range Attempts to reduce the propagation delay by lowering the interconnect capacitance (decreasing cross‐sectional dimensions) cause an increase in wire resistance which, in turn, increases the rise time and indirectly slows down the response Therefore, it is impossible to optimize VLSI and packaging interconnections to maximize the clock rate without analyzing losses (solving Helmholtz equation) and implementing lossy transmission line models This paper presents modeling and simulation of a gate array interconnect.