As speed and complexity of electronic systems increase, the interconnect density has become the critical limitation to the performance of electrical systems. The performance of computing and switching systems can be increased by optimizing the interconnect density and throughput. At the board to board level, electrical interconnects at high speeds require a bulky and expensive backplane. At the chip to chip area, the allocation of interconnects limits the performance of the chips. Electrical lossy lines limit the maximum interconnect distance due to reflections, risetime degradation, increased delay, attenuation and cross talk . Optical interconnects present the possibility of solving the interconnect problems by potentially achieving a high bandwidth and high volume density of channels. At high data rates (greater than 1 Gb/s) several channels may operate with negligible mutual interference.
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1 April 1993
Review Article|
April 01 1993
MODULE LEVEL PERFORMANCE SIMULATOR FOR ELECTRICAL AND OPTICAL INTERCONNECTS Available to Purchase
L. Guan;
L. Guan
CALCE Electronic Packaging Research Center University of Maryland College Park, MD 20742
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C. Pusarla;
C. Pusarla
CALCE Electronic Packaging Research Center University of Maryland College Park, MD 20742
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G. Halkias;
G. Halkias
CALCE Electronic Packaging Research Center University of Maryland College Park, MD 20742
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A. Christou
A. Christou
CALCE Electronic Packaging Research Center University of Maryland College Park, MD 20742
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Publisher: Emerald Publishing
Online ISSN: 2054-5606
Print ISSN: 0332-1649
© MCB UP Limited
1993
COMPEL (1993) 12 (4): 393–406.
Citation
Guan L, Pusarla C, Halkias G, Christou A (1993), "MODULE LEVEL PERFORMANCE SIMULATOR FOR ELECTRICAL AND OPTICAL INTERCONNECTS". COMPEL, Vol. 12 No. 4 pp. 393–406, doi: https://doi.org/10.1108/eb051813
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