To synthesize equivalent circuit obtained from reduced order model of large scale inductive PEEC circuits.
This paper describes an original approach for reducing and synthesizing large parasitic RLM electrical circuits coming from inductive Partial Element Equivalent Circuit (PEEC) models. The proposed technique enables the re-use of the reduced order model in the time domain circuit simulation context.
The paper shows how to use a synthesis method to realize an equivalent circuit issued from compressed PEEC circuits.
The coupling between methods PEEC and a compressed method as Fast Multipole Method (FMM) in order to reduce time and space consuming are well-known. The innovation here is to realise a smaller circuit equivalent with the original large scale PEEC circuits to use in temporal simulation tools. Moreover, this synthesis method reduces time and memories for modelling industrial application while maintaining high accuracy.
