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Emerging ‘chip‐size’packages, and bare flip‐chips, require new substrate properties if high lead count chips are to be reliably interconnected on printed wiring boards and multichip modules at low cost. Blind via holes have been shown to increase interconnect density significantly without adding layers which contribute to high cost. Until recently, the use of blind vias has been limited to high‐end applications since standard fabrication methods, either sequential lamination or controlled depth drilling, are too slow and expensive for most high volume commercial applications. To maintain a low layer count while interconnecting higher I/O packages, commercial and consumer electronics require a substrate technology which supports high speed, micro‐via hole formation. This paper describes a process for fabricating high speed micro‐vias in dimensionally stable non‐woven Aramid reinforced laminates using laser ablation technology. Laser equipment capable of producing over 100 blind micro‐via holes per second is discussed. The process steps of hole cleaning and plating are reviewed, showing how existing PWB manufacturing technologies can be used. This process is compared with other methods of generating small holes and blind vias in printed wiring boards. In addition, requirements for flip‐chip and chip‐size packages,including a coefficient of thermal expansion of <10 ppm/°C and thin laminate dimensional stability of <0.03%, are explained.

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