The purpose of this paper is to discuss nickel gold plating of PCB traces and its adverse effects on signal integrity, and to explore the other key drivers in optimising yields and controlling PCB processes that impinge on signal integrity.
The paper is a response to requests from PCB fabricators to explain why the losses on impedance controlled traces on PCBs were sometimes higher than expected.
While nickel is acceptable on short lengths of pad to accommodate gold plating, plating the whole trace length is generally not good practice from a digital signal integrity perspective. In addition, with the fastest serial transmission rates in the 10 to 20 GHz region and long serial words in some situations designers may need to consider both the associated high and low frequency performance.
With the development of ultra high speed digital bus architectures, PCB fabricators will appreciate the need to add an understanding of the drivers of insertion loss (base material loss tangent data, foil roughness and copper cross sectional areas) to their existing experience of architectures with minimal losses.
