Routing efficiency provides an estimate of the compactness of a specific PCB layout in comparison with the theoretical minimum size for the circuit design. This work describes a methodology for estimating the routing efficiency of existing PCB layouts from scanned images of either a manufactured PCB or the relevant PCB artwork. Measuring and maximising routing efficiency offers a powerful tool in the drive to minimise the size and cost of a PCB, as it provides a quantitative measure of the need to include costly features such as multiple signal layers and blind (or partial) vias.
The methodology was proven as a manual method, before implementation as a software tool. This work describes the image processing techniques used to recognise traces and vias and describes how this information is processed to derive substrate utilisation statistics.
An initial survey suggests that trace routing efficiency has declined through time, indicating that many layouts are larger than necessary, or use more signal layers than are required by routing constraints alone.
This work finds that digital logic circuits follow a more coherent trend than analogue or mixed technology circuits. The results are therefore much more applicable in the digital domain.
As the methodology is implemented using images of PCB layouts, it offers the potential to investigate the performance of routing capability for current and legacy applications where CAD data are not available.
Where CAD drawings exist, routing efficiency can easily be calculated from the data. However, the methodology for estimating routing efficiency retrospectively from circuit images is believed to be unique, and sidesteps the problems of gaining access to this information.
