Energy efficient IEEE 754 floating point multiplier using dual spacer delay insensitive logic Available to Purchase

The purpose of this paper is to present a single-precision floating-point multiplier where a low-power operation is attained through the reduction of switching activity. A floating-point multiplier is the basic building block for many applications such as digital signal processing (DSP) processors and multimedia applications involving a large dynamic range.

A floating-point multiplier was implemented in asynchronous logic such as multi-threshold null conventional logic and the proposed multi-threshold dual spacer dual rail delay insensitive logic (MTD³L). The proposed logic deals with high performance and energy efficiency.

The Institute of Electrical and Electronics Engineering (IEEE) has provided a standard to define the floating-point representation, which is known as the IEEE 754 standard. Rounding has not been implemented because it is not suitable for high-precision applications.

The performance aspects of the proposed asynchronous MTD³L floating-point multiplier are obtained using a Mentor Graphics tool and are compared with those of the existing asynchronous logic.