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Energy efficient IEEE 754 floating point multiplier using dual spacer delay insensitive logic

Circuit World (2017) 43 (2): 72–79.

https://doi.org/10.1108/CW-03-2017-0012

Published: 02 May 2017

... such as digital signal processing (DSP) processors and multimedia applications involving a large dynamic range. Design/methodology/approach A floating-point multiplier was implemented in asynchronous logic such as multi-threshold null conventional logic and the proposed multi-threshold dual spacer dual rail...

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