...Naresh Kattekola; Shubhankar Majumdar Purpose This paper aims to implement a novel design of approximate comparator which can be suitable for image processing applications. Design/methodology/approach Here, the N-bit approximate comparator is implemented by taking reference of N as 2-, 4...

..., and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs. Design/methodology/approach To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR...

... number of components and blocks. The proposed ultra-low-power circuit of the SAR-ADC consists of four major blocks, which include Bee-bootstrap, Spider-Latch dual comparator, dual SAR-logic and dual digital to analog converter. The authors have used the 90-nm CMOS library for the construction...