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Energy efficient IEEE 754 floating point multiplier using dual spacer delay insensitive logic

Circuit World (2017) 43 (2): 72–79.

https://doi.org/10.1108/CW-03-2017-0012

Published: 02 May 2017

... Sudhakar Jyothula can be contacted at: sudhakar.jyo@gmail.com 15 03 2017 25 03 2017 04 04 2017 © Emerald Publishing Limited 2017 Emerald Publishing Limited Licensed re-use rights only Low power Asynchronous Dual rail Normalize In the early 1970s, the major...

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