Recent Advances in Testing Techniques for AI Hardware Accelerators

Emerging device technologies such as silicon photonics, nonvolatile memories, and heterogeneous monolithic 3D (M3D) integration are being explored as post-Moore’s law alternatives for achieving high-density integration of many-core AI accelerators. In addition to innovations at the device level, architectural optimizations are also being carried out to achieve high-performance processing of large AI workloads with custom accelerator hardware. Systolic array-based inferencing accelerators achieve higher throughput and improved energy efficiency compared to CPUs and GPUs because of the homogeneous and regular data flow in systolic arrays. However, the performance of such emerging AI accelerators can be adversely affected by faults due to process variations, manufacturing defects, and aging. In this monograph, we analyze the performance of several emerging AI accelerators in the presence of different uncertainties and present low-cost methods to assess the significance of faults and mitigate their effects. We show that across all technologies, the functional criticality of faults can vary significantly based on the fault type, fault location, and the application workload. The fault criticality assessment and mitigation techniques presented in this monograph are necessary for enabling low-cost test, diagnosis, and design of robust AI accelerators.