Systolic Array Design for Low‐level Image Processing Available to Purchase

Systolic array designs of parallel algorithms for low‐level digital image processing, and in particular the gradient operator, are described. Indicates how, to achieve high performance, a new systolic array can be designed in which all the cells in a double pipeline are interconnected to a system bus. The transputer implementation of the design is also considered and comments and conclusions that relate to the use of the systolic array on transputer networks are given. Subsequently it is shown that the systolic array design can be extended to handle the Prewitt and Sobel operators.