The paper aims to deal with a tuning method to reduce warpage of microelectronic substrates.
There are three major processes involved in this method: calculating effective thermomechanical properties of substrates with simple regular electric artworks using 3D finite element (FE) analyses; fitting simplified expressions to the results from the FE analyses; and developing 2D FE models of substrates with arbitrarily complicated artwork using the simplified expressions. These three processes were used to estimate the warpage. An optimization procedure through iterative searches was used to obtain optimized trace widths and/or spacing in order to reduce the warpage.
Using a printed circuit board design to prove our concept, it was found that the warpage could be significantly reduced by modifying trace widths and/or spacing of the printed circuit board.
The paper focuses on a tuning method to reduce warpage of microelectronic substrates.
