In the past 10 years, excessive research enthusiasm has been focused on 2.5D/3D advanced packaging (e.g. CoWoS/SoIC) used for data-center artificial intelligence (AI) chips and high bandwidth memory integration. For the edge AI chips with lightweight computing power, very thin FBGA (VFBGA), low power double data rate 5/5X (LPDDR5/5X) and wafer-level (WL) packaging with the redistribution layer (RDL)-first process are the integration technology trends. This paper focuses on AI system on chip (SoC) and LPDDR5X on-package integration design only using 3 RDL on the WL package. This paper aims to examine the influence to explore the trace routing scheme and corresponding signal integrity (SI) performance of the RDL interconnection for the on-package LPDDR5X, thereby providing RDL design and simulation reference for the ever-increasing demand for AI SoC and LPDDR5X on-package integration that is an alternative for on-board interconnection.
A design practice is used with type selection design and physical design. SI design and SI simulation are used to ensure the performance of the design practice. Detailed approach for the SI analysis consists of frequency domain and time domain simulation that are transmission line characteristics with coupled frequency domain and eye diagram analysis in the time domain.
Through the design practice and SI simulation analysis, VFBGA LPDDR5X and RDL-first technology are suitable for integration with AI SoC using WL packaging. Sub-10 µm line width and space design rule is required for the practice. The on-package integration SI performance is higher than that of on-board.
This paper is a technology application exploration and focuses on the design and SI simulation field. The main value is two-fold: on one side, providing a new solution for AI SoC and LPDDR5X integration; on the other side, extending the application range for WL packaging technology. The design and simulation results are valuable for the reference with the similar application.
