... efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA). Design/methodology/approach The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize...

... architectures operating at higher sampling frequency, was proposed in this work. The die was fabricated in 180 nm CMOS process technology with a supplied voltage of 1.8 V. Findings Measured results showed that the DNL and INL errors are within −1 to +1 LSB and −0.9 to +0.9 LSB, respectively for the input...

...Hyung-won Kim; Hyeim Jeong; Junho Yu; Chan-Soo Lee; Nam-Soo Kim Purpose This paper aims to propose a low-power complementary MOS (CMOS) current sensor for control circuit in an integrated DC-DC buck converter. Design/methodology/approach The integrated DC-DC converter, which is composed...

... on either N_F or W_F only. CMOS Integrated circuits Maximum oscillation frequency Millimeter-wave Radio frequency Transistor Finger width Number of fingers S-parameter Maximum stable gain Siti Maisurah Mohd Hassan can be contacted at: maisurah...

... operation. Findings – The simulation test in 0.35 μm CMOS process shows that the charge pump regulator and DC-DC boost converter are accurately controlled with the variation of number of stages and duty ratio. The output-voltage is obtained to be 6-15 V within the ripple ratio of 5 percent...

...Joon Huang Chuah; David Holburn Purpose The purpose of this paper is to design a very low‐noise transimpedance amplifier (TIA) for a novel multi‐pixel CMOS photon detector which performs secondary electron (SE) detection in the scanning electron microscope (SEM). Design/methodology/approach...