Mapping full‐systolic arrays for matrix product on XILINX's XC4000(E,EX) FPGAs

Matrix product is a compute bound problem that can be efficiently handled by elementary systolic algorithms. From a theoretical point of view, most of the algorithms are very simple and sometimes even trivial. However, the task of designing efficient implementation on a fixed‐connection network, such as on FPGA where resources are very limited, has been more demanding, and sometimes quite tedious. The objective of this paper is twofold: we first describe a full‐systolic algorithm for matrix product that has the merit over its existing counterparts, to require no preloading of input data into elementary processors (EPs) and generates output data only from boundary EPs. The resulting architecture can accept an uninterrupted stream of input data and produces an uninterrupted one with a latency of 2N‐1 for N×N matrix product. This architecture is also scalable and complies with the constraint of problem‐size independence (ψ). Secondly, we present a methodology for generating a family of very compact MP arrays on FPGA based essentially upon manual mapping at CLB level coupled with VHDL structural level.