The prompt measurements of variation in phase, amplitude and frequency of a sinusoidal signal are crucial in a complex electrical network system. A Phasor measurement unit (PMU) uses a phasor estimation technique to estimate the phasor of the voltage and current signals, frequency and rate-of-change of frequency. The phasor estimation technique must adhere to the compliance requirements mentioned in the IEC/IEEE 60255-118-1 Standard. It is observed that fulfilling the IEEE compliance is a challenging task with a low sampling rate. This paper aims to develop a phasor estimation technique fulfilling the performance criteria at low sampling frequency.
To provide high accuracy during off-nominal frequency estimation, this work attempts to enrich the attenuation level at the side-lobe using a five-term cosine function, namely, an enriched side-lobe suppressor (ESS). It enhances the phasor estimation in the interpolation discrete Fourier transform (IpDFT) technique to achieve the performance requirements at a low sampling rate.
The performance of the proposed ESS-IpDFT technique is evaluated under the static and dynamic compliance specified in the IEC/IEEE 60255-118-1 Standard. The ESSIpDFT complies with the M-class performance requirements by maintaining the performance indices within the limits specified in the Standard. In addition, the performance of the ESSIpDFT approach is compared with the recently reported studies and found to offer better performance in most of the test indices.
A five-term cosine function-based ESS is designed to enrich the DFT interpolation for phasor estimation. The ESS-IpDFT based phasor estimation has been validated rigorously according to the IEC/IEEE 60255-118-1 Standard and compared with recently reported works.
