Flip‐chip assembly, developed in the early 1960s, is now being positioned as a key joining technology to achieve high‐density mounting of electronic components on to printed circuit boards for high‐volume, low‐cost products. Computer models are now being used early within the product design stage to ensure that optimal process conditions are used. These models capture the governing physics taking place during the assembly process and they can also predict relevant defects that may occur. Describes the application of computational modelling techniques that have the ability to predict a range of interacting physical phenomena associated with the manufacturing process. For example, in the flip‐chip assembly process we have solder paste deposition, solder joint shape formation, heat transfer, solidification and thermal stress. Illustrates the application of modelling technology being used as part of a larger UK study aiming to establish a process route for high‐volume, low‐cost, sub‐100‐micron pitch flip‐chip assembly.
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1 March 2002
Research Article|
March 01 2002
Using computer models to identify optimal conditions for flip‐chip assembly and reliability Available to Purchase
Christopher Bailey;
Christopher Bailey
Centre for Numerical Modelling and Process Analysis, School of Computing and Mathematical Sciences, University of Greenwich, London, UK
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Hua Lu;
Hua Lu
Centre for Numerical Modelling and Process Analysis, School of Computing and Mathematical Sciences, University of Greenwich, London, UK
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Greg Glinski;
Greg Glinski
Centre for Numerical Modelling and Process Analysis, School of Computing and Mathematical Sciences, University of Greenwich, London, UK
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Daniel Wheeler;
Daniel Wheeler
Centre for Numerical Modelling and Process Analysis, School of Computing and Mathematical Sciences, University of Greenwich, London, UK
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Phil Hamilton;
Phil Hamilton
Celestica Limited, Stoke‐on‐Trent, UK
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Mike Hendriksen;
Mike Hendriksen
Celestica Limited, Stoke‐on‐Trent, UK
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Brian Smith
Brian Smith
Celestica Limited, Stoke‐on‐Trent, UK
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Publisher: Emerald Publishing
Online ISSN: 1758-602X
Print ISSN: 0305-6120
© Company
2002
Circuit World (2002) 28 (1): 14–20.
Citation
Bailey C, Lu H, Glinski G, Wheeler D, Hamilton P, Hendriksen M, Smith B (2002), "Using computer models to identify optimal conditions for flip‐chip assembly and reliability". Circuit World, Vol. 28 No. 1 pp. 14–20, doi: https://doi.org/10.1108/03056120210696658
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Suggested Reading
Optimisation modelling for flip‐chip solder joint reliability
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Soldering & Surface Mount Technology (April,2003)
No flow underfill: additional reliability and failure mode analysis
Microelectronics International (August,2002)
Reliability of flip chips on FR‐4 assembled with reduced process steps
Circuit World (September,2001)
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