A VLSI Systolic Implementation of a String Pattern Matcher — Part I

In Part I of this article, surveys of the architectural concepts involved in designing special‐purpose VLSI computing structures are given. This leads to a discussion of systolic array, wavefront array, WARP and CHiP architectures and their applications. The INMOS transputer chip design and the parallel language OCCAM are introduced. The authors believe that together they form a modular hardware/software component of the type which is essential in the construction of highly parallel computer systems. (Part II of this article will consider the soft simulation of systolic algorithms via OCCAM and the systolisaion of the pattern matching problem).