The purpose of this paper is to reduce the reconfiguration time of a field‐programmable gate array (FPGA).
The paper focuses on introducing a new temporal placement algorithm which uses a typical mathematical formalism to optimize the reconfiguration time.
Results show that the algorithm decreases considerably the reconfiguration time compared with famous temporal placement algorithms.
The paper proposes a new temporal placement algorithm which optimizes reconfiguration time of modules on the device. The studied evaluation cases show that the proposed algorithm provides very significant results in terms reconfiguration time of modules versus other well‐known algorithms used in the temporal placement field. The authors uses the eigenvalue of the Laplacian matrix.
