Prior 12T hybrid SRAM cells offer high stability but introduce practical limitations like high control overhead and complex layouts, hindering large-array integration. This paper aims to propose a novel 12T topology overcoming these VLSI challenges while delivering exceptionally fast read operations.
A novel 12T hybrid tunnel field-effect transistor (TFET)-fin field-effect transistor (FinFET) SRAM is proposed. Unlike prior work focused on N-TFET pull-down paths, it introduces an innovative stacked four-PTFET pull-up network. The cell is validated using 20 nm InAs TFET and predictive technology model for multi-gate FinFET in simulation.
The architecture eliminates column-based write-assist signals, significantly reduced control complexity, while stacked PTFETs enable area-efficient device overlapping. Leveraging FinFETs in a decoupled read path, the cell achieves an exceptional 24 ps read latency at 0.6 V – outperforming 8T_S and HF_10T cells by approximately 130× and approximately 20×, respectively. Additionally, it secures the highest HSNM and RSNM among evaluated topologies (11% RSNM gain over recent 12T designs) and reduces leakage power by three orders of magnitude compared to the reference O_7T cell by effectively eliminating TFET reverse-bias currents.
This work presents the first hybrid 12T topology that resolves critical control-overhead and layout limitations while simultaneously shattering the read-speed bottleneck of TFET-based memories.
