This paper aims to examine the thermal cycling fatigue life performance of two-common solder array configurations, full and peripheral, using three-dimensional nonlinear finite element analysis.
The finite element simulations were used to identify the location of the critical solder interconnect, and using Darveaux's model, solder thermal fatigue life was computed.
The results showed that the solder array type does not significantly influence thermal fatigue life of the interconnect. However, smaller size packages result in improved life by almost 45% compared to larger package designs. Additionally, this paper provided an engineered study on the effect of the number of rows available in a perimeter array component on solder thermal fatigue performance.
General design recommendations for reliable electronic assemblies under thermal cycling loaded were offered in this research.
