The purpose of this paper is to propose a solution procedure to minimize/eliminate voiding and spattering defects in the assembly of 0201 chip components with micro via‐in pads and 95 wt.%Sn‐5 wt.%Sb solder alloy.
In total, four different micro via‐in pad designs were compared (via‐hole opening size): ultra small via‐in pads (d: 10 μm), small via‐in pads (d: 20 μm), and large via‐in pads (d: 60 μm), as well as designs with no via‐in pads and capped via‐in pads. Two process variables were also evaluated for the goal of achieving a high‐yield assembly solution in micro via‐in pad and lead‐free solder systems. Potential factors, such as the preheat conditions of the reflow profile and stencil aperture size, which might affect voiding and spattering in solder joints with micro via‐in pad, were investigated. Solder voiding frequency and size were also determined from X‐ray inspection and sample cross‐section analysis.
The results indicated that larger via‐holes were seen to create bigger voiding than smaller via‐holes. For smaller via‐holes, spattering is a greater problem than voiding in solder joints. Ultra small via‐in pads generated higher spattering compared to no via‐in pads and capped via‐in pads. Capped via‐in pads exhibited the best results in preventing voiding and flux spattering, and provided a wide process window for the selection of process parameters. It is also indicated that spattering was found to rapidly reduced with both increasing stencil opening size and use of reflow profile with long‐preheat conditions.
The findings provide certain process guidelines for surface‐mount assembly with via‐in pad substrate design. The strategy is to prevent voiding and spattering by adopting capped via‐in pads, if possible, when applying micro via with the 95 wt.%Sn‐5 wt.%Sb solder alloy system.
