AN EFFICIENT RESPONSE SURFACE TECHNIQUE FOR INVESTIGATING CMOS PROCESS RELATED EFFECTS ON CIRCUIT ELECTRICAL PERFORMANCE

The ability to simulate the effects of process technology on final product circuits has become virtually indispensable in modern VLSI production. It is especially significant as a toot for controlling parametric yield by appropriate design centering and in determining the sensitivity of the electrical parameters to process control tolerances. The system demands the combined use of process simulation device simulation and circuit simulation all three of which rely heavily on computationally intensive numerical solution of partial differential equations. The severe computational overhead involved in ‘technology simulation TCAD)’ means it is generally expensive and limits the scope of statistical design centering and optimisation, which depend on a large number of simulations. A compromise solution is often resorted to by limiting simulation to one or two spatial dimensions, replacing numerical simulation by analytical approximations as implemented in the statistical process simulator: FABRICS 11, or combining numerical and analytical models as in the process/device simulator PRIDE.) This paper addresses the problem of simpler, higher efficiency TCAD evaluation by restricting the domain of the simulation and approximating the process/device characteristic relationship by a set of simple, computationally efficient empirical equations. These equations offer a high speed solution at the expense of decreasing accuracy away from the nominal process centre. Referred to as a ‘response surface model’, it is generated using the results of a small number of statistically designed TCAD simulations. As the process sample is centred around the nominal design parameters, the model can be used to statistically analyze the effects of process perturbations.