Synopsys, Altera and TSMC collaborate to deliver Silicon-accurate parasitic modeling and extraction for 28-nm processes

Article Type: Industry news From: Microelectronics International, Volume 29, Issue 3

Synopsys, Inc. has collaborated with Altera and TSMC to silicon-validate modeling of key parasitic effects in Synopsys’ StarRC™ solution for TSMC’s 28-nm processes. The StarRC solution achieved the stringent model-to-silicon accuracy criteria of TSMC’s 28-nm process technology to enable high-performance designs at the advanced node. Altera Corporation, a pioneer in programmable logic, has successfully deployed StarRC to achieve signoff accurate extraction and accelerate the design cycle of its 28-nm FPGA designs.

At advanced nodes (28-nm and below), process modeling complexity has increased significantly due to continued transistor scaling, the increasing number of metal and dielectric layers, new device structures and the increased field effects between devices and interconnects. Several second-order effects that could be ignored in the past must now be accurately modeled and extracted to ensure desired circuit behavior. StarRC offers silicon-accurate modeling for the new 28-nm process effects as validated by foundries and customers on their taped-out designs. StarRC’s key 28-nm features include: modeling of increased conductor width variation due to advanced retargeting and optical-proximity-correction (OPC) effects, via-faceting and coupling effects of larger via shapes; area-dependent via resistance and capacitance; and enhanced layout-dependent device parasitic extraction. In addition, the StarRC solution includes the Rapid3D field solver technology for fast, high-accuracy 3D extraction that is also qualified by TSMC for the 28-nm node.

Web site: www.synopsys.com