Improving the fatigue life of a bare die flip chip by thinning Available to Purchase

The solder joint reliability of FC components on organic substrates is questionable unless underfill is used to relieve the thermal strains. Besides the mechanical protection, underfill provides the solder and I.C. surface with protection against the environment. Underfilling is however, time‐consuming and expensive. In an electrical sense, the underfill has no beneficial function and should, therefore, be considered as a ballast in an electronic assembly. However, to obtain a satisfactory level of reliability without underfill some novel methods are required. Wafer thinning is often performed to fit a die into a thin package, e.g. in smart cards. In this paper, the issue of thinning a package is studied utilizing 3D finite element method models. Various die and board thicknesses are evaluated with respect to their effect on the reliability of FC solder bumps. In addition, a novel idea to increase the joint reliability is studied.