Electronics - the history of the future
Electronics the history of the future
The push for personal computer performance to move from 25Mhz to 50Mhz in volume production took almost two years to achieve, 1994/1995. During that period it was necessary to use all kinds of performance enhancers such as on-module voltage pumps, balanced interconnect and innovative bus structures to preserve signal integrity.
The move from 50Mhz to 200Mhz was then achieved in less than one year and onwards to 333Mhz a half year after that. All of this was achieved by two areas of technological expenditure,namely that of containing power consumption by reducing voltage levels, and by reduced feature sizes. I refer to this achievement as "technological expenditure" because there is naturally a finite limit on both of these resources. It is my belief that these resources have not necessarily been spent wisely in the continual battle by the technology leaders for marketplace position.
Reduced voltage levels
Voltage levels as a resource are easily understood, the history has been a logical progression, as is the future; 5 volts became 3.3 volts, logical in that this is 3 Nicad batteries. The next move was then on down to 2.7 volts, derived on the silicon itself from the 3.3 volts for easy management. The next move is to 2.2 volts,being two Nicads and ultimately this will reduce to 1.1 volts.
The implications of this"technological expenditure" fall mainly with the interconnect fabricator. The signal switching levels are already so low that designers are forced to consider two traces to connect point to point. This technique is referred to as"differential interconnect" and a great deal of work has been done on this subject to provide tools for tomorrow's designers. The technology is based on differentiating the noise to leave a clean signal. The interconnect fabricator has the task of achieving either perfectly balanced lines (exactly the same length) or of producing buried resistors to act as line terminators. Either way the tolerances are not easy to meet, will only get more difficult, and nobody will be prepared to pay! The expenditure of this technology now leaves almost nowhere to go for a future interconnect based on electron transmission.
Reduced feature size
The feature sizes I refer to are those on the silicon, the time to reduce from ten microns to one micron was a matter of a dozen or so years, the time to reduce from 1 micron to 0.25 micron has been a matter of one tenth of that time. This "technological expenditure" has achieved all of the short term benefits perceived by the end user, but has expended the technology at such a rate that there is only one more step which can be taken without bumping into natural barriers. This step is from 0.25 microns down to 0.15 microns. To get the true "last ditch" gain from this expenditure it is essential that the jump from 400+Mhz to 1GHz is achieved. Silicon geometries are such that below 0.15 microns the oxide insulation layers are so thin that they become porous and stop acting as insulators. Also below 0.15 microns the transistors become so small that they would only hold a few(less than ten) electrons, half of which we would probably lose on the way and the other half would not be conducive to any gain. Hence the need to make best possible use of this "technological expenditure".
The history of electronics
From the above it is clear to see that electronics for high performance are running rapidly up to natural barriers which will slow, if not stop, the progression seen in the last 20 or so months and will no longer be able to satisfy the clamour for more and more performance.
Moores' Law was expected to continue up to the year 2000 when 100 million transistors/chips would be realised and CMOS technology was expected to see us through to about 2010. Recent developments in SiGe give greater flexibility to designers of digital/analogue mixed circuits, but do nothing to address these basic natural barriers.
So what about the short term future, the next 36 to 48 months? Clearly we will have expended two of our best technological assets as voltages cannot go lower and geometries can not go smaller. All that is left is to make the devices bigger and bigger in area. This initially will give rise to a rapid increase in I/O pins (already in October 1998 we have devices with in excess of 1,900 pins!). However, it is very unlikely that this rise in I/O count will become the third "technological expenditure" to become a natural barrier to progress. Just as printed circuit layer counts went up to 30 plus layers in the early days of gate array technology, so the large area device will peak on I/O count and then fall back again as the devices become more and more of a "system on a chip". These large devices will initially be supported by high performance differential interconnect utilising flip chip on board (FCOB) technologies.
Very large devices, which will be effectively the system on a chip, will keep the electron harnessed as our IT motivation force through to, possibly, as late as 2010. So what happens then? What will be our prime moving force when electronics are simple history?We are looking at a change similar to that from steam to diesel in the 1900s,but on 10 per cent of the timescale.
Professor Phil G.B. HamiltonTechnology ManagerCelestica LimitedPhamilto@celestica.com
