...Calvin Ling; Aizat Abas; Cheng Kai Chew; Muhammad Taufik Azahari Purpose This study aims to develop an empirical model to elucidate the void size formed during an underfilling process of asymmetrical ball grid array flip-chip of I, L and U dispensing orientation with various parameters. Design...

...Calvin Ling; Cheng Kai Chew; Aizat Abas; Taufik Azahari Purpose This paper aims to identify a suitable convolutional neural network (CNN) model to analyse where void(s) are formed in asymmetrical flip-chips with large amounts of the ball-grid array (BGA) during underfilling. Design/methodology...

...Calvin Ling; Muhammad Taufik Azahari; Mohamad Aizat Abas; Fei Chong Ng Purpose This paper aims to study the relationship between the ball grid array (BGA) flip-chip underfilling process parameter and its void formation region. Design/methodology/approach A set of top-down scanning acoustic...

...Fei Chong Ng; Aizat Abas; Muhammad Naqib Nashrudin; M. Yusuf Tura Ali Purpose This paper aims to study the filling progression of underfill flow and void formation during the flip-chip encapsulation process. Design/methodology/approach A new parameter of filling progression that relates volume...

...Yong‐Won Lee; Keun‐Soo Kim; Katsuaki Suganuma Purpose The purpose of this paper is to propose a solution procedure to minimize/eliminate voiding and spattering defects in the assembly of 0201 chip components with micro via‐in pads and 95 wt.%Sn‐5 wt.%Sb solder alloy. Design/methodology/approach...

... of voids in the interconnecting eutectic solder balls of these packages. Large voids can affect the mechanical and thermal properties of the interconnect, which can reduce a component’s mean time‐to‐failure and may also affect the transmission of high frequency electrical signals through the solder ball...