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Journal Articles

Low-level logic fault testing ASIC simulation environment

Mansour Assaf, Leslie-Ann Moore, Sunil Das, Satyendra Biswas, Scott Morton

World Journal of Engineering (2014) 11 (3): 279–286.

https://doi.org/10.1260/1708-5284.11.3.279

Published: 01 June 2014

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Journal Articles

On automated test system for asymmetric digital subscriber line equipment

Tariq Syed, Sunil Das, Satyendra Biswas, Mansour Assaf, Emil Petriu

World Journal of Engineering (2013) 10 (4): 387–394.

https://doi.org/10.1260/1708-5284.10.4.387

Published: 01 December 2013

View article titled, On automated test system for asymmetric digital subscriber line equipment

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Journal Articles

Energy efficient optimization of wireless embedded sensor networks

Mansour Assaf, Salema Khan, Sunil Das, Satyendra Biswas

World Journal of Engineering (2013) 10 (3): 273–282.

https://doi.org/10.1260/1708-5284.10.3.273

Published: 01 September 2013

View article titled, Energy efficient optimization of wireless embedded sensor networks

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Journal Articles

Response compression in space with cascade of two-input linear and nonlinear logic

Sunil Das, Alexander Applegate, Satyendra Biswas, Emil Petriu

World Journal of Engineering (2013) 10 (3): 283–296.

https://doi.org/10.1260/1708-5284.10.3.283

Published: 01 September 2013

View article titled, Response compression in space with cascade of two-input linear and nonlinear logic

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Journal Articles

Fault-tolerance in VLSI systems design using data compression under constraints of failure probabilities-overview and current status

Sunil Das, Satyendra Biswas, Emil Petriu, Voicu Groza, Mansour Assaf, Amiya Nayak

World Journal of Engineering (2013) 10 (1): 73–84.

https://doi.org/10.1260/1708-5284.10.1.73

Published: 01 March 2013

View article titled, Fault-tolerance in VLSI systems design using data compression under constraints of failure probabilities-overview and current status

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Journal Articles

Implementing built-in self-test environment for cores-based digital circuits with Verilog HDL

Sunil Das, Liwu Jin, Mansour Assaf, Satyendra Biswas, Emil Petriu

World Journal of Engineering (2012) 9 (6): 519–528.

https://doi.org/10.1260/1708-5284.9.6.519

Published: 01 December 2012

View article titled, Implementing built-in self-test environment for cores-based digital circuits with Verilog HDL

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Journal Articles

Cascade of two-input nonlinear logic in designing space compression networks in VLSI

Sunil Das, Satyendra Biswas, Voicu Groza, Mansour Assaf

World Journal of Engineering (2012) 9 (3): 199–206.

https://doi.org/10.1260/1708-5284.9.3.199

Published: 01 June 2012

View article titled, Cascade of two-input nonlinear logic in designing space compression networks in VLSI

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Low-level logic fault testing ASIC simulation environment

On automated test system for asymmetric digital subscriber line equipment

Energy efficient optimization of wireless embedded sensor networks

Response compression in space with cascade of two-input linear and nonlinear logic

Fault-tolerance in VLSI systems design using data compression under constraints of failure probabilities-overview and current status

Implementing built-in self-test environment for cores-based digital circuits with Verilog HDL

Cascade of two-input nonlinear logic in designing space compression networks in VLSI

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