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Purpose

Portable electronic products are often subjected to fumble and fall during use. The purpose of this study is to investigate the reliability of the chip power temperature loads while being subjected to drop impact loads.

Design/methodology/approach

In this study, the influence of five different chip power sizes on the Sn0.3Ag0.5Cu (SAC305) solder joints in Package-on-Package (POP) structures under thermal-drop impact load is systematically investigated. The board-level POP package structure is modeled using finite element analysis software COMSOL, and the temperature distribution within the structure is simulated by applying thermal power loads. This temperature field serves as the boundary condition for subsequent analyses, while the drop impact load is applied through the Input-G method. As a result, the stress distribution of the solder joints in the POP packages under thermal-drop impact loading is determined. Furthermore, the relationship between the maximum peeling stress of the solder joints and the maximum number of drops is established based on the power law principle. Finally, the life prediction of critical solder joints is achieved.

Findings

The findings reveal that solder joint 3 of the U2A component in the POP package is the most critical solder joint, with its stress level being a key determinant of the package’s vulnerability to damage under thermal-drop impact loading conditions. The most pronounced effect on the lifetime of solder joints under thermal-drop impact loading was observed when the chip power ranged from 1 to 1.4 W. It is crucial to consider the influence of power on POP packages under thermal-drop impact loading conditions during electronic design, especially when the power falls within the range of 1–1.4 W.

Originality/value

The maximum peeling stress of corner solder joint 3 in POP packages can serve as a failure criterion for the optimization of electronic product design. When electronic products incorporating POP packages are subject to handling or are prone to dropping, it is essential to minimize the power to 0 or, to the greatest extent feasible, to limit it to less than 1 W.

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