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Purpose
In this short communication, transition times of input signals for various stages of a repeater‐chain loaded VLSI interconnects are studied.
Design/methodology/approach
SPICE simulations.
Findings
It is observed that for a fixed number of repeaters a smaller load will reduce transition time. The effect is not very significant, if the load is moderate.
Originality/value
Method can be very useful for short‐circuit power estimation in repeater‐chains.
© Emerald Group Publishing Limited
2005
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